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NXP Semiconductors Electronic Components Datasheet

LF298 Datasheet

Sample-and-hold amplifiers

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Philips Semiconductors Linear Products
Sample-and-hold amplifiers
Product specification
LF198/LF298/LF398
DESCRIPTION
The LF198/LF298/LF398 are monolithic sample-and-hold circuits
which utilize high-voltage ion-implant JFET technology to obtain
ultra-high DC accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, DC gain accuracy is 0.002%
typical and acquisition time is as low as 6µs to 0.01%. A bipolar
input stage is used to achieve low offset voltage and wide
bandwidth. Input offset adjust is accomplished with a single pin and
does not degrade input offset drift. The wide bandwidth allows the
LF198 to be included inside the feedback loop of 1MHz op amps
without having stability problems. Input impedance of 1010allows
high source impedances to be used without degrading accuracy.
P-channel junction FETs are combined with bipolar devices in the
output amplifier to give droop rates as low as 5mV/min with a 1µF
hold capacitor. The JFETs have much lower noise than MOS
devices used in previous designs and do not exhibit high
temperature instabilities. The overall design guarantees no
feedthrough from input to output in the hold mode even for input
signals equal to the supply voltages.
Logic inputs are fully differential with low input current, allowing
direct connection to TTL, PMOS, and CMOS; differential threshold is
1.4V. The LF198/LF298/LF398 will operate from ±5V to ±18V
supplies. They are available in 8-pin plastic DIP, 8-pin Cerdip, and
14-pin plastic SO packages.
FEATURES
Operates from ±5V to ±18V supplies
Less than 10µs acquisition time
TTL, PMOS, CMOS compatible logic input
0.5mV typical hold step at CH=0.01µF
Low input offset
0.002% gain accuracy
Low output noise in hold mode
Input characteristics do not change during hold mode
High supply rejection ratio in sample or hold
Wide bandwidth
PIN CONFIGURATIONS
FE, N Packages
V+ 1
OFFSET VOLTAGE 2
INPUT 3
V– 4
8 LOGIC
7 LOGIC REFERENCE
6 Ch
5 OUTPUT
TOP VIEW
D1 Package
INPUT 1
NC 2
V– 3
NC 4
NC 5
NC 6
OUTPUT 7
14 VOS Adj
13 NC
12 V+
11 LOGIC
10 LOGIC REF
9 NC
8 Ch
TOP VIEW
NOTE:
1. SO and non-standard pinouts.
APPLICATION
The LF198/LF298/LF398 are ideally suited for a wide variety of
sample-and-hold applications, including data acquisition,
analog-to-digital conversion, synchronous demodulation, and
automatic test setup
ORDERING INFORMATION
DESCRIPTION
8-Pin Ceramic Dual In-Line Package (CERDIP)
14-Pin Plastic Small Outline (SO) Package
8-Pin Ceramic Dual In-Line Package (CERDIP)
8-Pin Plastic Dual In-Line Package (DIP)
8-Pin Ceramic Dual In-Line Package (CERDIP)
8-Pin Plastic Dual In-Line Package (DIP)
TEMPERATURE RANGE
-55°C to +125°C
0 to +70°C
0 to +70°C
0 to +70°C
-25°C to +85°C
-25°C to +85°C
ORDER CODE
LF198FE
LF398D
LF398FE
LF398N
LF298FE
LF298N
DWG #
0580A
0175D
0580A
0404B
0580A
0404B
August 31, 1994
879 853-0135 13721


NXP Semiconductors Electronic Components Datasheet

LF298 Datasheet

Sample-and-hold amplifiers

No Preview Available !

Philips Semiconductors Linear Products
Sample-and-hold amplifiers
Product specification
LF198/LF298/LF398
FUNCTIONAL DIAGRAM
OFFSET
3
INPUT
8
LOGIC
LOGIC 7
REFERENCE
30k
+
300
6
HOLD
CAPACITOR
TYPICAL APPLICATIONS
5
OUTPUT
3
ANALOG INPUT
SAMPLE 5V
HOLD 0V
LOGIC
INPUT
V+
V–
1
4
5
S/H
6
OUTPUT
7
8
Ch
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
VS Supply voltage
Maximum power dissipation
TA=25°C (still-air)3
F package
±18 V
780 mW
N package
1160
mW
D package
1040
mW
TA
TSTG
VIN
Operating ambient temperature range
LF198
LF298
LF398
Storage temperature range
Input voltage
-55 to +125
-25 to +85
0 to +70
-65 to +150
Equal to
supply voltage
°C
°C
°C
°C
Logic-to-logic reference differential
voltage2
+7, -30
V
Output short-circuit duration
Indefinite
Hold capacitor short-circuit duration
10 sec
TSOLD
Lead soldering temperature (10sec max)
300 °C
NOTES:
1. The maximum junction temperature of the LF398 is 150°C. When operating at elevated ambient temperature, the packages must be derated
based on the thermal resistance specified.
2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins must always be at least 2V
below the positive supply and 3V above the negative supply.
3. Derate above 25°C, at the following rates:
F package at 6.2mW/°C
N package at 9.3mW/°C
D package at 8.3mW/°C
August 31, 1994
880


Part Number LF298
Description Sample-and-hold amplifiers
Maker NXP
Total Page 5 Pages
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