900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




NXP Semiconductors Electronic Components Datasheet

GTL16612 Datasheet

18-bit GTL/GTL to LVTTL/TTL bidirectional latched translator 3-State

No Preview Available !

INTEGRATED CIRCUITS
GTL16612
18-bit GTL/GTL+ to LVTTL/TTL
bidirectional latched translator (3-State)
Product specification
1999 Sep 13
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

GTL16612 Datasheet

18-bit GTL/GTL to LVTTL/TTL bidirectional latched translator 3-State

No Preview Available !

Philips Semiconductors
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
latched translator (3-State)
Product specification
GTL16612
FEATURES
18-bit bidirectional bus interface
Translates between GTL/GTL+ logic levels (B ports) and
LVTTL/TTL logic levels (A ports)
5 V I/O tolerant on the LVTTL/TTL side (A ports)
No bus current loading when LVTTL/TTL output is tied to 5 V bus
3-State buffers
Output capability: +64 mA/-32 mA on the LVTTL/TTL side
(A ports); +40 mA on the GTL side (B ports)
TTL input levels on control pins
Power-up reset
Power-up 3-State
Positive edge triggered clock inputs
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
DESCRIPTION
The GTL16612 is a high-performance BiCMOS product designed for
VCC operation at 3.3 V with I/O compatibility up to 5 V.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
CI/O
ICCZ
Propagation delay
An to Bn or Bn to An
Input capacitance (Control pins)
I/O pin capacitance
Total supply current
CONDITIONS
Tamb = 25°C
CL = 50 pF
VI = 0 V or VCC
Outputs disabled; VI/O = 0 V or VCC
Outputs disabled
TYPICAL
3.3 V
1.9
4
8
12
UNIT
ns
pF
pF
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
ORDER CODE
GTL16612 DGG
DWG NUMBER
SOT364-1
1999 Sep 13
2 853–2166 22326


Part Number GTL16612
Description 18-bit GTL/GTL to LVTTL/TTL bidirectional latched translator 3-State
Maker NXP
Total Page 12 Pages
PDF Download

GTL16612 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 GTL16612 18-bit GTL/GTL to LVTTL/TTL bidirectional latched translator 3-State
NXP





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy