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CBTW28DD14 - 14-bit Bus Switch/multiplexer

General Description

This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS select input levels.

It is designed for operation in DDR2, DDR3 or DDR4 memory bus systems.

Key Features

  • 2.1 Topology.
  • 14-bit bus width.
  • 1 : 2 switch/MUX topology.
  • Bidirectional operation.
  • Simple CMOS select pin (SEL).
  • Simple CMOS enable pin (EN) 2.2 Performance.
  • 2.5 GHz bandwidth.
  • Low ON insertion loss.
  • Low crosstalk.
  • High OFF isolation.
  • POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling NXP Semiconductors CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CBTW28DD14 14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications Rev. 7.1 — 3 August 2015 Product data sheet 1. General description This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltage operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS select input levels. It is designed for operation in DDR2, DDR3 or DDR4 memory bus systems. The CBTW28DD14 has a 1 : 2 switch or 2 : 1 multiplex topology and offers a 14-bit wide bus. Each 14-bit wide A-port can be switched to one of two ports B and C, for all bits simultaneously. The selection of the port is by a simple CMOS input (SELect). Another CMOS input (ENable) is available to allow all ports to be disconnected.