80C51 Overview
The 8xC51 and 8xC52 contain a 128 × 8 RAM and 256 × 8 RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor munications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device is a low power static design which offers a wide range of operating frequencies...
80C51 Key Features
- 8051 Central Processing Unit
- 4k × 8 ROM (80C51)
- 8k × 8 ROM (80C52)
- 128 × 8 RAM (80C51)
- 256 × 8 RAM (80C52)
- Three 16-bit counter/timers
- Boolean processor
- Full static operation
- Low voltage (2.7 V to 5.5 V@ 16 MHz) operation
- Memory addressing capability
