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74LVC373A - Octal D-type transparent latch

General Description

The 74LVC373A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications.

A latch enable input (pin LE) and an output enable input (pin OE) are common to all internal latches.

Key Features

  • 5 V tolerant inputs/outputs for interfacing with 5 V logic.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • High-impedance outputs when VCC = 0 V.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-B exceeds 200 V.
  • CDM JESD22-C101E exceeds.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVC373A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 3 — 22 November 2012 Product data sheet 1. General description The 74LVC373A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable input (pin LE) and an output enable input (pin OE) are common to all internal latches. When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes. When pin LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of pin LE.