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74HCT4094 - 8-stage shift-and-store bus register

Download the 74HCT4094 datasheet PDF. This datasheet also covers the 74HC4094 variant, as both devices belong to the same 8-stage shift-and-store bus register family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Key Features

  • Complies with JEDEC standard JESD7A.
  • Input levels:.
  • For 74HC4094: CMOS level.
  • For 74HCT4094: TTL level.
  • Low-power dissipation.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2 000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Specified from 40 C to +85 C and from 40 C to +125 C 3.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC4094-NXP.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74HCT4094 8-stage shift-and-store bus register nexperia
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74HCT4094D 8-stage shift-and-store bus register nexperia
74HCT4094DB 8-stage shift-and-store bus register nexperia
74HCT4002 Dual 4-input NOR gate nexperia

Other Datasheets by NXP Semiconductors

Part Number Description
74HCT4002 Dual 4-input NOR gate
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74HCT4002D-Q100 Dual 4-input NOR gate
74HCT40105 4-bit x 16-word FIFO register
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC4094; 74HCT4094 8-stage shift-and-store bus register Rev. 7 — 10 February 2016 Product data sheet 1. General description The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow.