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74HCT165 - 8-bit parallel-in/serial out shift register

Download the 74HCT165 datasheet PDF. This datasheet also covers the 74HC165 variant, as both devices belong to the same 8-bit parallel-in/serial out shift register family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with JEDEC standard no.

7A.

They are pin compatible with Low-power Schottky TTL (LSTTL).

Features

  • I Asynchronous 8-bit parallel load I Synchronous serial input I Complies with JEDEC standard no. 7A I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from.
  • 40 °C to +85 °C and from.
  • 40 °C to +125 °C 3.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC165-NXP.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74HCT165 8-bit parallel-in/serial out shift register nexperia
74HCT165-Q100 8-bit parallel-in/serial out shift register nexperia
74HCT165D 8-bit parallel-in/serial out shift register nexperia
74HCT160 Presettable synchronous BCD decade counter Philips
74HCT161 Presettable synchronous 4-bit binary counter Philips

Other Datasheets by NXP Semiconductors

Part Number Description
74HCT164 8-bit serial-in / parallel-out shift register
74HCT11 Triple 3-input AND gate
74HCT123 Dual retriggerable monostable multivibrator
74HCT123-Q100 Dual retriggerable monostable multivibrator
74HCT125 Quad buffer/line driver

Full PDF Text Transcription

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74HC165; 74HCT165 8-bit parallel-in/serial out shift register Rev. 03 — 14 March 2008 Product data sheet 1. General description The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition.
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