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NXP Semiconductors Electronic Components Datasheet

74ALVC16836A Datasheet

20-bit registered driver

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INTEGRATED CIRCUITS
74ALVC16836A
20-bit registered driver with
inverted register enable (3-State)
Product specification
Replaces datasheet 74ALVC16836 of 2000 Jan 04
IC24 Data Handbook
2000 Mar 14
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

74ALVC16836A Datasheet

20-bit registered driver

No Preview Available !

Philips Semiconductors
20-bit registered driver with inverted register enable
(3-State)
Product specification
74ALVC16836A
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Output drive capability 50 transmission lines @ 85°C
Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC16836A is a 20-bit universal bus driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
Y7
GND
Y8
Y9
Y10
Y11
Y12
Y13
GND
Y14
Y15
Y16
VCC
Y17
Y18
GND
Y19
Y20
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 CP
55 A1
54 A2
53 GND
52 A3
51 A4
50 VCC
49 A5
48 A6
47 A7
46 GND
45 A8
44 A9
43 A10
42 A11
41 A12
40 A13
39 GND
38 A14
37 A15
36 A16
35 VCC
34 A17
33 A18
32 GND
31 A19
30 A20
29 LE
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
SH00197
TYPICAL
tPHL/tPLH
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
VCC = 3.3 V, CL = 50 pF
2.3
2.6
2.5
fmax Maximum clock frequency
VCC = 3.3 V, CL = 50 pF
CI Input capacitance
CI/O Input/Output capacitance
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
transparent mode
Output enabled
Output disabled
Clocked mode
Output enabled
Output disabled
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
350
4.0
8.0
13
3
22
15
UNIT
ns
MHz
pF
pF
pF
2000 Mar 14
2 853–2194 23314


Part Number 74ALVC16836A
Description 20-bit registered driver
Maker NXP
Total Page 12 Pages
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