74ABT16501A Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS 74ABT16501A 74ABTH16501A 18-bit universal bus transceiver (3-State) Product specification Supersedes data of 1997 Jun 12 IC23 Data Handbook 1998 Feb 27 Philips Semiconductors Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) 74ABT16501A 74ABTH16501A Features - 18-bit bidirectional bus interface - 3-State buffers - Output capability: +64m A/-32m A - TTL input and output switching levels - 74ABTH16501A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs DESCRIPTION The 74ABT16501A high-performance Bi CMOS device bines low static and dynamic power dissipation with high speed and high output drive. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus patible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are plimentary (OEAB is active High, and OEBA is active Low). Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Two options are available, 74ABT16501A which does not have the bus-hold feature and 74ABTH16501A which incorporates the bus-hold feature. - Live insertion/extraction permitted - Power-up reset - Power-up 3-State - Positive edge-triggered clock inputs - Latch-up protection exceeds 500m A per JEDEC Std 17 - ESD protection exceeds 2000V per MIL...