UPD160300 Overview
The µ PD160300 is a high-withstanding-voltage CMOS driver designed for use with a flat display panel such as a PDP, VFD, or EL panel. It consists of a 192-bit bi-directional shift register, 192-bit latch and high-withstanding-voltage CMOS driver. The logic block operates with a 5.0 V power supply and 3.3 V interface so that it can be directly connected to a gate array and microputer (CMOS Level Input).
UPD160300 Key Features
- 3-ch, 6-ch and 6-ch (3-ch + 3-ch) input port switching is possible using the IBS1 and IBS2 pins
- Many outputs: 192-bit output
- Clock transfer is switchable via the SDS pin between single edge and double edge
- Data control with transfer clock (external) and latch
- High-speed data transfer: fCLK = 60 MHz MAX. (at loading of data)
- High withstanding voltage and high drive output: 80 V MAX., +13/-24 mA MAX
- 3.3 V input interface (VDD1 = 5.0 V)
- High-withstanding-voltage CMOS structure