UPD6379A Datasheet | NEC

FEATURES - Resistor string conversion method - 0-point digital shift circuit - × 4 oversampling Sampling frequency: 200 k Hz MAX. - Signal processing format for 2’s plement, MSB first, and backward justification data acmodated - Left and right in-phase output - High performance (at VDD = +5.0 V) S/N ratio: 100 d B TYP. Dynamic range: 96 d B TYP. - Low-voltage models available - Bipolar LR clock (LRCK) - Low power dissipation: 10 m W TYP. (with µPD6379L, 6379AL at VDD = +3.3 V) LRCK Supply voltage +3.3 V (VDD = +3.0 to 5.5 V) +5.0 V (VDD = +4.5 to 5.5 V) LRCK = L when L-ch data is input LRCK = H when L-ch data is input µPD6379L µPD6379 µPD6379AL µPD6379A - Few external ponents Internal output operational amplifier Only one electrolytic capacitor required for smoothing reference voltage, instead of two capacitors required by existing D/A converters - Small package: 8-pin plastic SOP (5.72 mm (225)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S11588EJ4V0DS00 (4th edition) Date Published November 1999 N CP(K) Printed in Japan The mark shows major revised points. © µPD6379, 6379A, 6379L, 6379AL ORDERING INFORMATION Part number Package 8-pin plastic SOP (5.72 mm (225)) 8-pin plastic SOP (5.72 mm (225)) 8-pin plastic SOP (5.72 mm (225)) 8-pin plastic SOP (5.72 mm (225)) µPD6379GR µPD6379LGR µPD6379AGR µPD6379ALGR BLOCK DIAGRAM L. OUT Main DAC Shift register latch LRCK Timing generator Sub DAC GND Sub DAC Main DAC R. OUT Data Sheet S11588EJ4V0DS00 µPD6379, 6379A, 6379L, 6379AL PIN CONFIGURATIONS (Top View) 8-pin plastic SOP (5.72 mm (225)) - µPD6379GR, 6379LGR LRCK SI CLK...