UPD44324092 Datasheet | NEC

.. DATA SHEET MOS INTEGRATED CIRCUIT µPD44324082, 44324092, 44324182, 44324362 36M-BIT DDRII SRAM 2-WORD BURST OPERATION Description The µPD44324082 is a 4,194,304-word by 8-bit, the µPD44324092 is a 4,194,304-word by 9-bit, the µPD44324182 is a 2,097,152-word by 18-bit and the µPD44324362 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44324082, µPD44324092, µPD44324182 and µPD44324362 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA. Features - 1.8 ± 0.1 V power supply - 165-pin PLASTIC BGA package (13 x 15) - HSTL Interface - DLL circuitry for wide output data valid window and future frequency scaling - Pipelined double data rate operation - mon data input/output bus - Two-tick burst for low DDR transaction size - Two input clocks (K and K#) for precise DDR timing at clock rising edges only - Two output clocks (C and C#) for precise flight time and clock skew matching-clock and data delivered together to receiving device - Internally self-timed write control - Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed. - User programmable impedance output <R> - Fast clock cycle time : 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz) - Simple control logic for easy depth expansion - JTAG boundary scan The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative...