UPD161830 Datasheet | NEC

DESCRIPTION The µ PD161830 is a source driver for TFT-LCDs supporting 64 gray-scale display and can operate with a supply voltage of 2.5 V for the logic block and 5.0 V for the driver block. Data input as 6-bit x 3-dot digital data is output as 64 γ -corrected values using an internal D/A converter and 5 external power modules, thus achieving a 260,000-color (full-color) display. FEATURES - CMOS level input - 240 outputs - Input of 6 bits (gray-scale data) by 3 dots - Capable of outputting 64 values by means of 5 external power modules and a D/A converter - Output dynamic range: VSS2 to VDD2 - High-speed data transfer: f CLK = 15 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.5 V) - Level inversion γ -correction power supply is possible - Logic power supply voltage (VDD1): 2.2 to 3.6 V - Driver power supply voltage (VDD2): 4.5 to 5.5 V ORDERING INFORMATION Part Number .. Package Chip µ PD161830P Remark Purchasing the above chip entail the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives. The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S16240EJ2V0PM00 (2nd edition) Date Published July 2002 NS CP (K) Printed in Japan The mark # shows major revised points. © µPD161830 1. BLOCK DIAGRAM STHL VDD1(2.5 V) VSS1 C79 C80 STHR R,/L CLK INV D00 to D05 D10 to D15 D20 to D25 C1 C2 80-bit bidirectional shift register INBUF Data register CM STB POL Mode control AP MODE VCsel V Latch V BUF Level shifter VDD2 (5.0 V) VSS2 V0 to V4 GAM VDD1 TESTIN TESTO1 TESTO2 γ...