CS5828 Datasheet | Myson Technology

DESCRIPTION The CS5828 receives four sets of 7-bit data in CMOS logic level and converts them into four lowvoltage differential signaling (LVDS) serial channels. The 7-bit input data is referenced to the CKIN signal. The RF pin selects either rising or falling edge trigger of CKIN. Parallel to serial conversion is performed by a 7X internal generated clock reference using onchip PLL using CKIN. A copy of CKIN but phaselocked to the output serial streams, CLKOUT, is also converted to the fifth LVDS channel. The CS5828 offers a reliable munication media using LVDS signaling and provides low EMI dealing with wide, high-speed TTL interfaces. This is especially attractive for interfaces between GUI controller and display systems such as LCD panels for SVGA/XGA/SXGA applications. FEATURES - Four 7-bit serial and one clock LVDS channels. - patible with ANSI TIA/EIA-644 LVDS standard. - Wide CKIN ranges from 31MHz to 85MHz. - Fully integrated on-chip PLL that provides 7X CKIN serial shift clock. - Pin selectable for rising or falling edge trigger. - Support power-down mode. - 5V/3.3V tolerant data input. - Single 3.3V supply operation. - CMOS low power consumption. - Functional patible with DS90C385. - Available in 56-pin TSSOP package. BLOCK DIAGRAM D0,D1,D2,D3, D4,D6,D7 . Data Shee SHIFT/LOAD_N CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y0P EN Y0N D8,D9,D12,D13, D14,D15,D18 SHIFT/LOAD_N CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y1P EN Y1N D19,D20,D21,D22, D24,D25,D26 PARALLEL-IN SERIAL-OUT EN Y2P Y2N SHIFT/LOAD_N 7-Bit SHIFT REGISTER CLK D27,D5,D10,D11, D16,D17,D23 SHIFT/LOAD_N CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y3P EN Y3N RF CKIN 7x CLK PHASE LOCK LOOP SHIFT/LOAD_N R/F CLK CKOP EN...