MUAA2K80M Datasheet | Music Semiconductors

om Data Sheet MUAAe Reto4Uu.tcing Co Processor (RCP) Family APPLICATION BENEFITS Sh- High performance MAC Address processor for tamultiport switches and routers (Up to 48 10/100 or 4 a Gigabit Ethernet at wire speed) .D- Layer 4 flow recognition for Quality of Service up to 16.7 million packets per second ww- ARP Cache manager/IP address caching at 12.5 w million packets per second m- Synchronous interfaces and programmable priority between ports for simplicity of design o- Learn, age, and auto-age functions with “virtual .cqueues,” keeping track of aged and learned entries - Transparent cascade of up to four 2K devices without t4Uexternal logic, software setup, or performance hit DISTINCTIVE CHARACTERISTICS - 2K and 8K x 80-bit partitionable CAM/RAM data field in address database - 32-bit synchronous port with separate inputs and outputs; optional 16-bit configuration - 32-bit bi-directional processor port; optional 16-bit configuration - Pipelined operation - Operations performed from the synchronous port or processor port; all flags independently available to both ports - 9-bit internal time stamp - 50 MHz clock - 388-pin PBGA (8K) and 160-pin PQFP (2K) packages. - 3.3 Volt core with 3.3 Volt/5 Volt tolerant IO buffers. - IEEE 1149.1 (JTAG) pliant Sync Port DIN(31:0) Processor Port DIN(31:0) OP(3:0) /DINE DINREADY .Data Shee PROCD(31:0) w PROCA(5:0) /PCS R/W PROCREADY w INT /RESET m CLK Control 16/32 to 80-bit mux 16/32 to 80-bit mux 80-bit latch 80-bit latch 80-bit 2 to 1 mux Address Data Base -- b i t 79 -- ------- ------- b i t 0--- Flag and Chain Logic /FF...