MC68EC040V Datasheet (PDF) Download
Motorola Semiconductor
MC68EC040V

Key Features

  • of the MC68EC040 include
  • 4-Kbyte Instruction Cache and 4-Kbyte Data Cache Accessible Simultaneously
  • 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Bursting Interface
  • Concurrent Integer Unit, ACU, and Bus Controller Operation Maximizes Throughput
  • Low-Latency Bus Accesses for Reduced Cache-Miss Penalty
  • Multimaster/Multiprocessor Support via Bus Snooping
  • The DLE and MDIS pin names have been changed to JS0 and JS1, respectively