MC68EC040V Description
w w S a t APPENDIX B a MC68EC040 .D w e e h U 4 t m o .c REV2.2 (11/02/99) NOTE Rev. 2.2 contains timing information for 40 MHz operation. Some TBD values will be filled in shortly.
MC68EC040V Key Features
- MC68040-patible Integer Execution Unit
- 4-Kbyte Instruction Cache and 4-Kbyte Data Cache Accessible Simultaneously
- 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Bursting Interface
- User-Object-Code patible with All M68000 Microprocessors
- Concurrent Integer Unit, ACU, and Bus Controller Operation Maximizes Throughput
- Low-Latency Bus Accesses for Reduced Cache-Miss Penalty
- Multimaster/Multiprocessor Support via Bus Snooping
- 4-Gbyte Direct Addressing Range
- Two independent access control units (ACUs) replace the MC68040 MMUs. The ACU has four corresponding registers (access c