68HC908MR32CB
Description
Figure 2-1. Memory Map
- Added FLASH Block Protect Register (FLBPR) at address location $FF7E 3 Figure A-1. MC68HC908MR16 Memory Map
- Added FLASH Block Protect Register (FLBPR) at address location $FF7E 4 19.4.3 Conversion Time
- Reworked equations and text for clarity. Figure 10-1. Monitor Mode Circuit
- PTA7 and connecting circuitry added Table 10-2. Monitor Mode Signal Requirements and Options
- Switch locations added to column headings for clarity 5 Section 11. Timer Interface A (TIMA)
- Timer discrepancies corrected throughout this section. Section 12. Timer Interface B (TIMB)
- Timer discrepancies corrected throughout this section. 199 225 388 346 187 189 Page Number(s) 41
August, 2001
October, 2001
December, 2001
Advance Information 4
MC68HC908MR16/MC68HC908MR32
- Rev. 5.0 MOTOROLA
Advance Information
- MC68HC908MR16/MC68HC908MR32
List of Sections
Section 1. General Description
- -
- - 29 Section 2. Memory Map
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