SN74LS323 register equivalent, 8-bit shift/storage register.
are described below:
1. They use eight D-type edge-triggered flip-flops that respond only to the LOW-to-HIGH transition of the Clock (CP). The only timing restriction, th.
* Input Clamp Diodes Limit High-Speed Termination Effects
* ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
V.
The logic diagram and truth table indicate the functional characteristics of the SN54/74LS323 Universal Shift/Storage Register. This device is similar in operation to the SN54/74LS299 except for synchronous reset. A partial list of the common feature.
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