SN74LS113A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Motorola Semiconductor (now NXP Semiconductors)

Download the SN74LS113A datasheet PDF. This datasheet also covers the SN74LS113D variant, as both devices belong to the same dual jk negative edge-triggered flip-flop family and are provided as variant models within a single manufacturer datasheet.

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SN74LS113A dual jk negative edge-triggered flip-flop by Motorola Semiconductor (now NXP Semiconductors) - Datasheet Preview — Note: The manufacturer provides a single datasheet file (SN74LS113D_MotorolaInc.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number	SN74LS113A
Manufacturer	Motorola Semiconductor (now NXP Semiconductors)
File Size	140.23 KB
Description	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Datasheet	SN74LS113A Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
SN74LS11	TRIPLE 3-INPUT POSITIVE-AND GATES	Texas Instruments
SN74LS112A	Dual J-K Negative-Edge-Triggered Flip-Flops	Texas Instruments
SN74LS10	TRIPLE 3-INPUT POSITIVE-NAND GATES	Texas Instruments
SN74LS10	TRIPLE 3-INPUT NAND GATE	ON Semiconductor
SN74LS107A	DUAL J-K FLIP-FLOPS	Texas Instruments

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number	Description
SN74LS11	TRIPLE 3-INPUT AND GATE
SN74LS112A	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS114A	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS10	TRIPLE 3-INPUT NAND GATE
SN74LS107A	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum setup times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.