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MTD20P03HDL - TMOS POWER FET

Features

  • slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbi.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTD20P03HDL/D ™ Data Sheet HDTMOS E-FET.™ High Density Power FET DPAK for Surface Mount Designer's MTD20P03HDL Motorola Preferred Device P–Channel Enhancement–Mode Silicon Gate This advanced HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
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