rmance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbe.
The following content is an automatically extracted verbatim text
from the original manufacturer datasheet and is provided for reference purposes only.
View original datasheet text
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MTB20N20E/D
™ Data Sheet TMOS E-FET.™ High Energy Power FET D2PAK for Surface Mount
Designer's
MTB20N20E
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time.
MTB20N20E Datasheet
