MPC9600 driver equivalent, low voltage 2.5 v and 3.3 v cmos pll clock driver.
* Multiplication of input frequency by 2, 3, 4 and 6
* Distribution of output frequency to 21 outputs organized in three output banks: QA0-QA6, QB0-QB6, QC0-QC6,.
Features:
* Multiplication of input frequency by 2, 3, 4 and 6
* Distribution of output frequency to 21 outputs.
Differential reference clock frequency input Reference clock input PLL feedback clock input Bank A outputs Bank B outputs Bank C outputs Differential feedback output Reference clock input select Selection of bank A output frequency Selection of bank .
Image gallery
TAGS
Download