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MC88920DW - LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

Datasheet Summary

Description

of the RST_IN/RST_OUT(LOCK) Functionality The RST_IN and RST_OUT(LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as a lock indicator.

up, the RST_OUT pin will be in the low state until steady state p

Features

  • mum 5.0 200 Unit ns ns.

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Datasheet preview – MC88920DW

Datasheet Details

Part number MC88920DW
Manufacturer Motorola
File Size 116.75 KB
Description LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature
Datasheet download datasheet MC88920DW Datasheet
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Full PDF Text Transcription

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document from Logic Marketing Low Skew CMOS PLL Clock Driver With Power-Down/Power-Up Feature The MC88920 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040 microprocessor family. The PLL allows the the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board.
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