differential PECL outputs as well as a choice between either a differential PECL clock input or a TTL clock input. The asynchronous master reset control is a PECL level i.

MC100H600

MC100H601

MC100H602

MC100H603

MC100H604

MC100H605

MC100H607

MC100H640

MC100H641

MC100H642

MC100H643

MC100H644

MC100H646

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