F801FA60 Datasheet | Motorola Semiconductor

Overview 1.1 56F801 Features .. - - - - - - - - - - - - - - Digital Signal Processing Core Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for pact code Efficient C piler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/On CE debug programming interface Freescale Semiconductor, Inc... - -...