F801FA60 - DSP56F801FA60

Motorola

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Datasheet Details

Part number	F801FA60
Manufacturer	Motorola
File Size	898.05 KB
Description	DSP56F801FA60
Datasheet	F801FA60_Motorola.pdf

F801FA60 Product details

Description

Eleven multiplexed General Purpose I/O (GPIO) pins Computer-Operating Properly (COP) watchdog timer One dedicated external interrupt pin External reset pin for hardware reset Emulation (OnCE™) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller core clock Oscillator flexibility between either an external crystal oscillator or an on-chip r

Features

www. datasheet4u. com 1.1.1.
Digital Signal Processing Core Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barr.

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Published: Jun 9, 2009 |