Datasheet4U Logo Datasheet4U.com

54LS256 - DUAL 4-BIT ADDRESSABLE LATCH

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
54LS256 Dual 4-Bit Addressable Latch National Semiconductor
54LS257A TRI-STATE Quad 2-Data Selectors/Multiplexers National Semiconductor
54LS257B Quad 2-Data Selectors/Multiplexers National Semiconductor
54LS257B QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS Texas Instruments
54LS258A TRI-STATE Quad 2-Data Selectors/Multiplexers National Semiconductor

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
54LS257B QUAD 2-INPUT MULTIPLEXER
54LS258B QUAD 2-INPUT MULTIPLEXER
54LS21 DUAL 4-INPUT AND GATE
54LS22 DUAL 4-INPUT NAND GATE
54LS26 QUAD 2-INPUT NAND BUFFER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DUAL 4-BIT ADDRESSABLE LATCH The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input (E) and an active LOW Clear input (CL). Each latch has a Data input (D) and four outputs (Q0 – Q3). When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs (Q0 – Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and E are both LOW. When CL is HIGH and E is LOW, the selected output (Q0 – Q3), determined by the Address inputs, follows D. When the E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address (A0, A1) could impose a transient wrong address.