PDSP16318 Datasheet | Mitel Networks Corporation

PDSP16318/16318A PDSP16318/PDSP16318A plex Accumulator Advance Information Supersedes version DS3708 - 2.4 September 1996 DS3708 - 3.1 November 1998 The PDSP16318/A contains two independent 20-bit Adder/Subtractors bined with accumulator registers and shift structures. The four port architecture permits full 20MHz throughout in FFT and filter applications. Two PDSP16318As bined with a single PDSP16112A plex Multiplier provide a plete arithmetic solution for a Radix 2 DIT FFT Butterfly. A new plex Butterfly result can be generated every 50ns allowing 1K plex FFTs to be executed in 256µs. GC100 Features s s s s s s s s s s s s s s Full 20MHz Throughout in FFT...