PDSP16256/A

Programmable FIR Filter

DS3709

Issue 7.1

June 1999

Features

q Sixteen MACs in a Single Device

q Basic Mode is 16-Tap Filter at up to 25MHz

Sample Rates

q Programmable to give up to 128 Taps with

Sampling Rates Proportionally Reducing to

3·125MHz

q 16-bit Data and 32-bit Accumulators

q Can be configured as One Long Filter or Two

Half-Length Filters

q Decimate-by-two Option will Double the Filter

Length

q Coefficients supplied from Host System or local

EPROM

Applications

q High Performance Digital Filters

Ordering Information

Commercial (0°C to 170°C)

PDSP16256A/C0/AC 25MHz, PGA package

Industrial (240°C to 185°C)

PDSP16256 B0/AC 20MHz, PGA package

PDSP16256 B0/GC 20MHz, QFP package

Military (255°C to 1125°C)

PDSP16256 MC/AC1R 20MHz, MIL-STD-883*

(latest revision), PGA package

PDSP16256 MC/GC1R 20MHz, MIL-STD-883*

(latest revision), QFP package

*See notes following Electrical Characteristics for further

information on MIL-STD-883 screening

Associated Products

PDSP16350 I/Q Splitter/NCO

PDSP16510A FFT Processor

Description

The PDSP16256 contains sixteen multiplier -

accumulators, which can be multi cycled to provide

from 16 to 128 stages of digital filtering. Input data

and coefficients are both represented by 16-bit

two’s complement numbers with coefficients

converted internally to 12 bits and the results being

accumulated up to 32 bits.

In 16-tap mode the device samples data at the

system clock rate of up to 25MHz. If a lower sample

rate is acceptable then the number of stages can be

increased in powers of two up to a maximum of 128.

Each time the number of stages is doubled, the

sample clock rate must be halved with respect to the

system clock. With 128 stages the sample clock is

therefore one eighth of the system clock.

In all speed modes devices can be cascaded to

provide filters of any length, only limited by the

possibility of accumulator overflow. The 32-bit

results are passed between cascaded devices

without any intermediate scaling and subsequent

loss of precision.

The device can be configured as either one long

filter or two separate filters with half the number of

taps in each. Both networks can have independent

inputs and outputs.

Both single and cascaded devices can be operated

in decimate-by-two mode. The output rate is then

half the input rate, but twice the number of stages

are possible at a given sample rate. A single device

with a 20MHz clock would then, for example,

provide a 128-stage low pass filter, with a 5MHz

input rate and 2·5MHz output rate.

Coefficients are stored internally and can be down

loaded from a host system or an EPROM. The latter

requires no additional support, and is used in stand

alone applications. A full set of coefficients is then

automatically loaded at power on, or at the request

of the system. A single EPROM can be used to

provide coefficients for up to 16 devices.