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Mitel Networks Corporation

PDSP16116AB0GG Datasheet Preview

PDSP16116AB0GG Datasheet

16 X 16 Bit Complex Multiplier

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Supersedes October 1996 version, DS3707 - 4.2
PDSP16116
16 X 16 Bit Complex Multiplier
DS3707 - 5.3 October 1997
The PDSP16116 contains four 16316 array multipliers, two
32-bit adder/subtractors and all the control logic required to sup-
port Block Floating Point Arithmetic as used in FFT applications.
The PDSP16116A variant will multiply two complex (16116)
bit words every 50ns and can be configured to output the com-
plete complex (32132) bit result within a single cycle. The data
format is fractional two’s complement.
In combination with a PDSP16318A, the PDSP16116A forms
a two-chip 20MHz complex multiplier accumulator with 20-bit
accumulator registers and output shifters. The PDSP16116A in
combination with two PDSP16318As and two PDSP1601As
forms a complete 20MHz Radix 2 DIT FFT butterfly solution
which fully supports block floating point arithmetic. The
PDSP16116 has an extremely high throughput that is suited to
recursive algorithms as all calculations are performed with a
single pipeline delay (two cycle fall-through).
FEATURES
I Complex Number (16116)3(16116) Multiplication
I Full 32-bit Result
I 20MHz Clock Rate
I Block Floating Point FFT Butterfly Support
I (21)3(21) Trap
I Two’s Complement Fractional Arithmetic
I TTL Compatible I/O
I Complex Conjugation
I 2 Cycle Fall Through
I 144-pin PGA or QFP packages
APPLICATIONS
I Fast Fourier Transforms
I Digital Filtering
I Radar and Sonar Processing
I Instrumentation
I Image Processing
ORDERING INFORMATION
PDSP16116 MC GGDR 10MHz MIL-883 screened
PDSP16116A B0 AC 20MHz Industrial
PDSP16116A A0 AC 20MHz Military
PDSP16116A B0 GG 20MHz Industrial
PDSP16116A MC GGDR 20MHz MIL-883 screened
PDSP16116B B0 AC 25MHz Industrial
PDSP16116D B0 GG 31·5MHz Industrial
XR15:0
XI15:0
YR15:0
YI15:0
REG REG REG REG
MULT
MULT
MULT
MULT
REG REG REG REG
ADD/SUB
ADD/SUB
SHIFT
SHIFT
REG REG
PR15:0
PI15:0
Fig. 1 Simplified block diagram
ASSOCIATED PRODUCTS
PDSP16318/A Complex Accumulator
PDSP16112/A (16116)3(12112) Complex Multiplier
PDSP16330/A Pythagoras Processor
PDSP1601/A ALU and Barrel Shifter
PDSP16350 Precision Digital Modulator
PDSP16256 Programmable FIR Filter
PDSP16510 Single Chip FFT Processor




Mitel Networks Corporation

PDSP16116AB0GG Datasheet Preview

PDSP16116AB0GG Datasheet

16 X 16 Bit Complex Multiplier

No Preview Available !

PDSP16116
SYSTEM FEATURES
The PDSP16116 has a number of features tailored for sys-
tem applications.
(21)3(21) Trap
In multiply operations using two’s complement fractional no-
tation, the (21)3(21) operation forms an invalid result because
11 is not representable in the fractional number range. The
PDSP16116 eliminates this problem by trapping the (21)3(21)
operation and forcing the multiplier result to become the most
positive representable number.
Complex Conjugation
Many algorithms using complex arithmetic require conjuga-
tion of complex data stream. This operation has traditionally re-
quired an additional ALU to multiply the imaginary component
by -1. The PDSP16116 eliminates this requirement by offering
on-chip complex conjugation of either of the two incoming com-
plex data words with no loss in throughput.
Easy Interfacing
As with all PDSP family members the PDSP16116 has reg-
istered l/O for data and control. Data inputs have independent
clock enables and data outputs have independent three state
output enables.
Signal
Type
Description
XR15:0
Xl15:0
YR15:0
Yl15:0
PR15:0
Pl15:0
CLK
CEX
CEY
CONX
CONY
ROUND
MBFP
SOBFP
EOPSS
AR15:1 3
Al15:1 3
WTA1:0
WTB1:0
WTOUT1:0
SFTA1:0
SFTR2:0
GWR4:0
OSEL1:0
OER, OEI
VDD
GND
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Power
Power
16-bit input for real X data
16-bit input for imaginary X data
16-bit input for real Y data
16-bit input for imaginary Y data
16-bit output for real P data
16-bit output for imaginary P data
Clock; new data is loaded on rising edge of CLK
Clock, enable X-port input register
Clock, enable Y-port input register
Conjugate X data
Conjugate Y data
Rounds the real and imaginary results
Mode select (BFP/Normal)
Start of BFP operations (see Note 1)
End of pass (See Note 1)
3 MSBs from real part of A-word (See Note 1)
3 MSBs from imaginary part of A-word (See Note 1)
Word tag from A-word
Word tag from B-word/shift control (See Note 2)
Word tag output (See Note 1)
Shift control for A-word / overflow flag (See Note 2)
Shift control for accumulator result (See Note 1)
Global weighting register contents (See Note 1)
Selects the desired output configuration
Output enables
15V Supply (See Note 3)
0V Supply (See Note 3)
NOTES
1. Used only in BFP mode
2. Performs different functions in BFP/Normal modes
3. All supply pins must be connected
Table 1 Signal descriptions
Normal
mode
configuration
Tie low
Tie low
Tie low
Tie low
Tie low
Tie low
2


Part Number PDSP16116AB0GG
Description 16 X 16 Bit Complex Multiplier
Maker Mitel Networks Corporation
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