PDSP16116AB0GG Overview
The PDSP16116A variant will multiply two plex (16116) bit words every 50ns and can be configured to output the plete plex (32132) bit result within a single cycle. The data format is fractional two’s plement. In bination with a PDSP16318A, the PDSP16116A forms a two-chip 20MHz plex multiplier accumulator with 20-bit accumulator registers and output shifters.