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Micross

MT5C2568 Datasheet Preview

MT5C2568 Datasheet

32K x 8 SRAM

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32K x 8 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-88662
•SMD 5962-88552
•MIL-STD-883
FEATURES
• Access Times: 12, 15, 20, 25, 35, 45, 55, 70, & 100ns
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS double-metal process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
OPTIONS
Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access1
70ns access1
100ns access
MARKING
-12
-15
-20
-25
-35
-45
-55
-70
-100
Package(s)2
Ceramic DIP (300 mil)
Ceramic DIP (600 mil)
Ceramic LCC (28 leads)
Ceramic LCC (32 leads)
Ceramic Flat Pack
Ceramic SOJ
C
CW
EC
ECW
F
DCJ
No. 108
No. 110
No. 204
No. 208
No. 302
No. 500
Operating Temperature Ranges
Military -55oC to +125oC
Industrial -40oC to +85oC
XT
IT
• 2V data retention/low power
L
NOTES:
1. Electrical characteristics identical to those provided for the
45ns access devices.
2. Plastic SOJ (DJ Package) is available on the AS5C2568 datasheet.
For more products and information
please visit our web site at
www.micross.com
MT5C2568 / AS5C2568
Rev. 4.7 10/11
SRAM
MT5C2568
AS5C2568
PIN ASSIGNMENT
(Top View)
28-PIN SOJ (DCJ)
28-Pin DIP (C, CW)
32-Pin LCC (ECW)
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ1 11
DQ2 12
DQ3 13
VSS 14
28 VCC
27 WE\
26 A13
25 A8
24 A9
23 A11
22 OE\
21 A10
20 CE\
19 DQ8
18 DQ7
17 DQ6
16 DQ5
15 DQ4
4 3 2 1 32 31 30
A6
A5
A4
A3
A2
A1
A0
NC
DQ1
5
6
7
8
9
10
11
12
13
29 A8
28 A9
27 A11
26 NC
25 OE\
24 A10
23 CE\
22 DQ8
21 DQ7
14 15 16 17 18 19 20
28-Pin LCC (EC)
28-Pin Flat Pack (F)
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ1 11
DQ2 12
DQ3 13
VSS 14
28 VCC
27 WE\
26 A13
25 A8
24 A9
23 A11
22 OE\
21 A10
20 CE\
19 DQ8
18 DQ7
17 DQ6
16 DQ5
15 DQ4
3 2 1 28 27
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
4
5
6
7
8
9
10
11
12
26 A13
25 A8
24 A9
23 A11
22 OE\
21 A10
20 CE\
19 DQ8
18 DQ7
13 14 15 16 17
GENERAL DESCRIPTION
The Micross Components SRAM family employs
high-speed, low power CMOS designs using a four-transistor
memory cell. These SRAMs are fabricated using double-layer
metal, double-layer polysilicon technology.
For exibility in high-speed memory applications, Mi-
cross Components offers chip enable (CE\) and output enable
(OE\) capability. These enhancements can place the outputs in
High-Z for additional exibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is
accomplished when WE\ remains HIGH and CE\ and OE\ go
LOW. The device offers a reduced power standby mode when
disabled. This allows system designs to achieve low standby
power requirements.
The “L” version provides a battery backup/low volt-
age data retention mode, offering 2mW maximum power dis-
sipation at 2 volts. All devices operate from a single +5V power
supply and all inputs and outputs are fully TTL compatible.
Micross Components reserves the right to change products or specications without notice.
1




Micross

MT5C2568 Datasheet Preview

MT5C2568 Datasheet

32K x 8 SRAM

No Preview Available !

FUNCTIONAL BLOCK DIAGRAM
SRAM
MT5C2568
AS5C2568
A0
DECODER
256 x 1024
MEMORY ARRAY
Vcc
GND
A14
I/O0
I/O
DATA
CIRCUIT
I/O7
CE\
OE\
CONTROL
CIRCUIT
WE\
COLUMN I/O
9A128-1
TRUTH TABLE
MODE
STANDBY
READ
READ
WRITE
OE\ CE\ WE\ DQ POWER
X H X HIGH-Z STANDBY
L L H Q ACTIVE
H L H HIGH-Z ACTIVE
X L L D ACTIVE
MT5C2568 / AS5C2568
Rev. 4.7 10/11
Micross Components reserves the right to change products or specications without notice.
2


Part Number MT5C2568
Description 32K x 8 SRAM
Maker Micross
PDF Download

MT5C2568 Datasheet PDF






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