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  Microsemi Electronic Components Datasheet  

ZL30361 Datasheet

Clock Network Synchronizer

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ZL30361
IEEE 1588 and Synchronous Ethernet Packet
Clock Network Synchronizer
Short Form Data Sheet
Features
• Frequency and Phase Sync over Packet Networks
• Frequency accuracy performance for WCDMA-
FDD, GSM, LTE-FDD and femtocell applications
• Frequency performance for ITU-T G.823 and
G.824 synchronization interface, as well as
G.8261 PNT PEC and CES interfaces
• Phase Synchronization performance for
WCDMA-TDD, Mobile WiMAX, TD-SCDMA and
CDMA2000 applications
• Client holdover and reference switching
between multiple Servers
• Physical Layer Equipment Clocks Synchronizatin
• ITU-T G.8262 for SyncE EEC option 1 and 2
• ITU-T G.813 for SONET/SDH SEC option 1 and
2
• Telcordia GR-1244 and GR-253 Stratum 3 and
SMC
• Support for G.781 SETS
May 2013
Ordering Information
ZL30361GDG2 144 Pin LBGA
Trays
Pb Free Tin/Silver/Copper
-40oC to +85oC
Package size: 13 x 13 mm
• Any input clock rate from 1 Hz to 750 MHz
• Automatic hitless reference switching and digital
holdover on reference fail
• Flexible two-stage architecture translates between
arbitrary data, line coding and FEC rates
• Digital PLL with programmable bandwidth from
0.1 mHz up to 1 kHz
• Programmable synthesizers
• Any output clock rate from 1Hz to 750MHz
• Output jitter below 0.62 ps rms
• Operates from a single crystal resonator or clock
oscillator
• Configurable via SPI/I2C interface
Osci
Osco
Ref0
Ref1
Ref2
Ref3
Ref4
Ref5
Ref6
Ref7
Ref8
Ref9
Ref10
Master Clock
Diff / Single Ended
Fr0= Br0*Kr0*Mr0/Nr0
Diff / Single Ended
Fr1= Br1*Kr1*Mr1/Nr1
Diff / Single Ended
Fr2= Br2*Kr2*Mr2/Nr2
Diff / Single Ended
Fr3= Br3*Kr3*Mr3/Nr3
Diff / Single Ended
Fr4= Br4*Kr4*Mr4/Nr4
Diff / Single Ended
Fr5= Br5*Kr5*Mr5/Nr5
Diff / Single Ended
Fr6= Br6*Kr6*Mr6/Nr6
Diff / Single Ended
Fr7= Br7*Kr7*Mr7/Nr7
Diff / Single Ended
Fr8= Br8*Kr8*Mr8/Nr8
Single Ended
Fr9= Br9*Kr9*Mr9/Nr9
Single Ended
Fr10= Br10*Kr10*Mr10/Nr10
JTAG
Reference Monitors
ZL30361
DPLL/NCO
Select Loop band.,
Phase slope limit
State
Machine
Configuration
and Status
Clock Generator 0
Synthesizer 0
Fs= Bs0*Ks0*16*Ms0/Ns0
Div A
Div B
Div C
Div D
Clock Generator 1
Synthesizer 1
Fs= Bs1*Ks1*16*Ms1/Ns1
Div A
Div B
Div C
Div D
Clock Generator 2
Synthesizer 2
Fs= Bs2*Ks2*16*Ms2/Ns2
Div A
Div B
Div C
Div D
LVPECL
LVPECL
LVCMOS
LVCMOS
LVPECL
LVPECL
LVCMOS
LVCMOS
LVPECL
LVPECL
LVCMOS
LVCMOS
hpdiff0_p/n
hpdiff1_p/n
hpoutclk0
hpoutclk1
hpdiff2_p/n
hpdiff3_p/n
hpoutclk2
hpoutclk3
hpdiff4_p/n
hpdiff5_p/n
hpoutclk4
hpoutclk5
JTAG
pwr_b
GPIO
SPI / I2C
Figure 1 - Functional Block Diagram
1
Copyright 2013, Microsemi Corporation. All Rights Reserved.


  Microsemi Electronic Components Datasheet  

ZL30361 Datasheet

Clock Network Synchronizer

No Preview Available !

ZL30361
Short Form Data Sheet
Detailed Features
General
• One clock channel
• Operates from a single crystal resonator or clock oscillator
• Configurable via its SPI/I2C interface
Time Synchronization Algorithm
• External algorithm controls software digital PLL to adjust frequency and phase alignment
• Frequency, Phase and Time Synchronization over IP, MPLS and Ethernet Packet Networks
• Frequency accuracy performance for WCDMA-FDD, GSM, LTE-FDD and femtocell applications, with target
performance less than ± 15 ppb.
• Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT EEC,
PNT PEC and CES interface specifications.
• Phase Synchronization performance for WCDMA-TDD, Mobile WiMAX, TD-SCDMA and CDMA2000
applications with target performance less than ± 1 s phase alignment.
• Time Synchronization for UTC-traceability and GPS replacement.
• Client reference switching between multiple Servers
• Client holdover when Server packet connectivity is lost
Electrical Clock Inputs
• Nine input references configurable as single ended or differential and two single ended input references
• Synchronize to any clock rate from 1 Hz to 750 MHz on differential inputs
• Synchronize to any clock rate from 1 Hz to 177.75 MHz on singled-ended inputs
• Any input reference can be fed with sync (frame pulse) or clock.
• Synchronize to sync pulse and sync pulse/clock pair.
• Flexible input reference monitoring automatically disqualifies references based on frequency and phase
irregularities
• LOS
• Single cycle monitor
• Precise frequency monitor
• Coarse frequency monitor
• Guard soak timer
• Per input clock delay compensation
Electrical Clock Engine
• Digital PLL filters jitter from 0.1 mHz up to 1 kHz
• Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
• Internal state machine automatically controls mode of operation (free-run, locked, holdover)
• Automatic hitless reference switching and digital holdover on reference fail
• Physical-to-physical reference switching
2
Microsemi Corporation


Part Number ZL30361
Description Clock Network Synchronizer
Maker Microsemi
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