Download the ZL30253 datasheet PDF.
This datasheet also covers the ZL30252 variant, as both devices belong to the same multiplier and jitter attenuator family and are provided as variant models within a single manufacturer datasheet.
General Description
5.
Key Features
Input Clocks.
Three inputs: two differential/CMOS, one CMOS.
Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS).
Inputs continually monitored for activity and frequency accuracy.
Full PDF Text Transcription for ZL30253 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
ZL30253. For precise diagrams, and layout, please refer to the original PDF.
Register Map: Section 6.2 Features • Input Clocks • Three inputs: two differential/CMOS, one CMOS • Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS) • I...
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Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS) • Inputs continually monitored for activity and frequency accuracy • Automatic or manual reference switching • Low-Bandwidth DPLL • Programmable bandwidth, 14Hz to 500Hz • Attenuates jitter up to several UI • Freerun or digital hold on loss of all inputs • Digitally controlled phase adjustment • Low-Jitter Fractional-N APLL and 3 Outputs • Any output frequency from <1Hz to 1035MHz • High-resolution fractional frequency conversion with 0ppm error • Easy-to-configure, encapsulated design requires no external VCXO or loop filter components • Each output has in
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ZL30253 Datasheet
