ZL30151
Features
- Input Clocks
- Three inputs, two differential/CMOS, one CMOS
- Any input frequency from 1k Hz to 650MHz (1k Hz to 300MHz for CMOS)
- Inputs continually monitored for activity and frequency accuracy
- Automatic or manual reference switching
- Low-Bandwidth DPLL
- Programmable bandwidth, 1Hz to 500Hz
- Attenuates jitter up to several UI
- Freerun or holdover on loss of all inputs
- Hitless reference switching
- High-resolution holdover averaging
- Digitally controlled phase adjustment
- Low-Jitter Fractional-N APLL and 3 Outputs
- Any output frequency from <1Hz to 650MHz
- High-resolution fractional frequency conversion with 0ppm error
- Easy-to-configure, encapsulated design requires no external VCXO or loop filter ponents
- Each output has independent dividers
- Output jitter is typically 0.16 to 0.28ps RMS (12k Hz-20MHz integration band)
- Outputs are CML or 2x CMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL
3-Input, 3-Output Any-to-Any Line Card PLL with...
