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EDI88512C - 512Kx8 Monolithic SRAM

Description

Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power (+5V ±10%) Ground Not Connected A0-18 WE# CS# OE# BLOCK DIAGRAM Memory Array Address Buffer Address Decoder I/O Circuits I/O0-7 Microsemi Corporation reserves the right to change products or specifications witho

Features

  •  512Kx8 bit CMOS Static.
  •  Random Access Memory.
  • Access Times of 70, 85, 100ns.
  • Data Retention Function (LP version).
  • TTL Compatible Inputs and Outputs.
  • Fully Static, No Clocks.
  •  32 lead JEDEC Approved Evolutionary Pinout.
  • Ceramic Sidebrazed 600 mil DIP (Package 9).
  • Ceramic SOJ (Package 140).
  •  Single +5V (±10%) Supply Operation The EDI88512C is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the J.

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EDI88512C 512Kx8 Monolithic SRAM, CMOS FEATURES  512Kx8 bit CMOS Static  Random Access Memory • Access Times of 70, 85, 100ns • Data Retention Function (LP version) • TTL Compatible Inputs and Outputs • Fully Static, No Clocks  32 lead JEDEC Approved Evolutionary Pinout • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic SOJ (Package 140)  Single +5V (±10%) Supply Operation The EDI88512C is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. Both the DIP and CSOJ packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128C. Pins 1 and 30 become the higher order addresses.
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