• 1N5283 THRU 1N5314 AVAILABLE IN JANHC AND JANKC
PER MIL-PRF-19500/463
• CURRENT REGULATOR CHIPS
• ALL JUNCTIONS COMPLETELY PROTECTED WITH SILICON DIOXIDE
• ELECTRICALLY EQUIVALENT TO 1N5283 THRU 1N5314
• CONSTANT CURRENT OVER WIDE VOLTAGE RANGE
• COMPATIBLE WITH ALL WIRE BONDING AND DIE ATTACH TECHNIQUES,
WITH THE EXCEPTION OF SOLDER REFLOW
CD5283
thru
CD5314
MAXIMUM RATINGS
Operating Temperature: -55°C to +175°C
Storage Temperature: -55°C to +175°C
Peak Operating Voltage: 100 VOLTS
ELECTRICAL CHARACTERISTICS @ 25°C, unless otherwise speci½ed
TYPE
NUMBER
CD5283
CD5284
CD5285
CD5286
CD5287
CD5288
CD5289
CD5290
CD5291
CD5292
CD5293
CD5294
CD5295
CD5296
CD5297
CD5298
CD5299
CD5300
CD5301
CD5302
CD5303
CD5304
CD5305
CD5306
CD5307
CD5308
CD5309
CD5310
CD5311
CD5312
CD5313
CD5314
REGULATOR CURRENT
lp (mA) @ VT = 25V
(Note 3)
NOM
MIN
MAX
0.22
0.198
0.242
0.24
0.216
0.264
0.27
0.243
0.297
0.30
0.270
0.330
0.33
0.297
0.363
0.39
0.351
0.429
0.43
0.387
0.473
0.47
0.423
0.517
0.56
0.504
0.616
0.62
0.558
0.682
0.68
0.612
0.748
0.75
0.675
0.825
0.82
0.738
0.902
0.91
0.819
1.001
1.00
0.900
1.100
1.10
0.990
1.210
1.20 1.08 1.32
1.30 1.17 1.43
1.40 1.26 1.54
1.50 1.35 1.65
1.60 1.44 1.76
1.80 1.62 1.98
2.00 1.80 2.20
2.20 1.98 2.42
2.40 2.16 2.64
2.70 2.43 2.97
3.00 2.70 3.30
3.30 2.97 3.63
3.60 3.24 3.96
3.90 3.51 4.29
4.30 3.87 4.73
4.70 4.23 5.17
MINIMUM
DYNAMIC
IMPEDANCE
@VT = 25V
ZT (M )
(Note 1)
25.0
19.0
14.0
9.0
6.6
4.10
3.30
2.70
1.90
1.55
1.35
1.15
1.00
0.880
0.800
0.700
0.640
0.580
0.540
0.510
0.475
0.420
0.395
0.370
0.345
0.320
0.300
0.280
0.265
0.255
0.245
0.235
MINIMUM
KNEE
IMPEDANCE
@VK = 6.0 V
ZK (M )
(Note 2)
2.75
2.35
1.95
1.60
1.35
1.00
0.870
0.750
0.560
0.470
0.400
0.335
0.290
0.240
0.205
0.180
0.155
0.135
0.115
0.105
0.092
0.074
0.061
0.052
0.044
0.035
0.029
0.024
0.020
0.017
0.014
0.012
MAXIMUM
LIMITING
VOLTAGE
@ lL = 0.8 lp (min)
VL (VOLTS)
1.00
1.00
1.00
1.00
1.00
1.05
1.05
1.05
1.10
1.13
1.15
1.20
1.25
1.29
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.75
1.85
1.95
2.00
2.15
2.25
2.35
2.50
2.60
2.75
2.90
NOTE 1
NOTE 2
NOTE 3
ZT is derived by superimposing A 90Hz RMS signal equal to 10% of VT on VT.
ZK is derived by superimposing A 90Hz RMS signal equal to 10% of VK on VK.
IP is read using a pulse measurement, 10 milliseconds maximum.
BACKSIDE IS CATHODE
A = Anode
DESIGN DATA
METALLIZATION:
Top: (Anode).......................Al
Back: (Cathode)..................Au
AL THICKNESS.......25,000 Å Min
GOLD THICKNESS...4,000 Å Min
CHIP THICKNESS.............10 Mils
TOLERANCES: ALL Dimensions
+ 2 mils, Except Anode Pad
Where Tolerance is + 0.1 mils.
6 L A K E S T R E E T , L A W R E N C E , M A S S A C H U S E T T S 01841
PHONE (978) 620-2600
FAX (978) 689-0803
WEBSITE: http://www.microsemi.com
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