MT54W4MH8B burst equivalent, sram 2-word burst.
* DLL circuitry for accurate output data placement
MT54W4MH8B MT54W4MH9B MT54W2MH18B MT54W1MH36B
Figure 1 165-Ball FBGA
* Separate independent read and write da.
that benefit from a high-speed, fully-utilized DDR data bus. Please refer to Micron’s Web site (www.micron.com/ sramds) .
4 Meg x 8, QDRIIb2 FBGA 4 Meg x 9, QDRIIb2 FBGA 2 Meg x 18, QDRIIb2 FBGA 1 Meg x 36, QDRIIb2 FBGA
OPTIONS
* Clock Cycle Timing 4ns (250 MHz) 5ns (200 MHz) 6ns (167 MHz) 7.5ns (133 MHz)
* Configurations 4 Meg x 8 4 Meg x 9 2 Meg x 18 1 Meg x .
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