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MT48LC16M16LF - 4M x 16 x 4 Banks MOBILE SDRAM

General Description

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Key Features

  • Fully synchronous; all signals registered on positive edge of system clock.
  • Internal pipelined operation; column address can be changed every clock cycle.
  • Internal banks for hiding row access/precharge.
  • Programmable burst lengths: 1, 2, 4, 8, or full page.
  • Auto Precharge, includes.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PRELIMINARY‡ 256Mb: x16 MOBILE SDRAM MOBILE SDRAM Features • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes • Self Refresh Mode • 64ms, 8,192-cycle refresh • LVTTL-compatible inputs and outputs • Low voltage power supply • Temperature Compensated Self Refresh (TCSR) Option Marking • VDD/VDDQ LC 3.3V/3.3V G 3.0V/3.0V V 2.5V/2.5V-1.