MT48H8M16LF
Key Features
- Fully synchronous; all signals registered on positive edge of system clock
- Internal pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access/precharge
- Programmable burst lengths: 1, 2, 4, 8, or full page
- Auto precharge, includes concurrent auto precharge, and auto refresh modes
- Self refresh mode; standard and low power
- 64ms, 4,096-cycle refresh
- LVTTL-compatible inputs and outputs
- Low voltage power supply
- Partial array self refresh power-saving mode
