MT41K128M8 Description
Refer to the DDR3 (1.5V) SDRAM data sheet specifications when running in 1.5V patible mode.
MT41K128M8 Key Features
- VDD = VDDQ = +1.35V (1.283V to 1.45V)
- Backward patible to VDD = VDDQ = 1.5V ±0.075V
- Differential bidirectional data strobe
- 8n-bit prefetch architecture
- Differential clock inputs (CK, CK#)
- 8 internal banks
- Nominal and dynamic on-die termination (ODT)
- Programmable CAS (READ) latency (CL)
- Programmable CAS additive latency (AL)
- Programmable CAS (WRITE) latency (CWL)