MT2854M16B1LL Datasheet | Micron Technology

FEATURES MT28S4M16B1LL - 1 Meg x 16 x 4 banks MT28S2M32B1LL - 512K x 32 x 4 banks - 125 MHz SDRAM-patible read timing - Fully synchronous; all signals registered on positive edge of system clock - Internal pipelined operation; column address can be changed every clock cycle - Internal banks for hiding row access - Programmable burst lengths: 1, 2 , 4, 8, or full page (read) 1, 2, 4, or 8 (write) - LVTTL-patible inputs and outputs - 3.0V- 3.6V VCC, 1.65V- 1.95V VCCQ Additional VHH hardware protect mode (RP#) - Supports CAS latency of 1, 2, and 3 - Four-bank architecture supports true concurrent operation with zero latency Read any bank while programming or erasing any other bank - Deep power-down mode: 50µA (MAX) - Cross-patible Flash memory mand set . - Operating temperature range of -40o C to +85o C PIN ASSIGNMENT (Top View) 90-Ball FBGA - 2 Meg x 32 1 A B C D E F G H J K L M N P R DQ26 DQ24 Vcc DQ23 DQ21 DQ28 Vcc Q VSSQ Vcc Q VSSQ DQ19 VSSQ DQ27 DQ25 DQ22 DQ20 Vcc...