MT2854M16B1LL
Overview
- 125 MHz SDRAM-compatible read timing
- Fully synchronous; all signals registered on positive edge of system clock
- Internal pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access
- Programmable burst lengths: 1, 2 , 4, 8, or full page (read) 1, 2, 4, or 8 (write)
- LVTTL-compatible inputs and outputs
- 3.0V-3.6V VCC, 1.65V-1.95V VCCQ Additional VHH hardware protect mode (RP#)
- Supports CAS latency of 1, 2, and 3
- Four-bank architecture supports true concurrent operation with zero latency Read any bank while programming or erasing any other bank
- Deep power-down mode: 50µA (MAX)
