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46V32M16 - MT46V32M16

General Description

The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.

It is internally configured as a quadbank DRAM.

The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation.

Key Features

  • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V.
  • Bidirectional data strobe (DQS) transmitted/ received with data, i. e. , source-synchronous data www. DataSheet4U. com capture (x16 has two.
  • one per byte).
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle.
  • Differential clock inputs (CK and CK#).
  • Commands entered on each positive CK edge.
  • DQS edge-aligned with data for READs; centeraligned with data for WRIT.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ADVANCE‡ 512Mb: x4, x8, x16 DDR SDRAM DOUBLE DATA RATE (DDR) SDRAM FEATURES • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data www.DataSheet4U.com capture (x16 has two – one per byte) • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask (DM) for masking write data (x16 has two – one per byte) • Programmable burst lengths: 2, 4, or 8 • x16 has programmable IOL/IOV.