MT9HTF6472PZ
Key Features
- 240-pin, registered dual in-line memory module
- Supports ECC error detection and correction
- VDD = VDDQ = 1.8V
- VDDSPD = 1.7-3.6V
- Differential data strobe (DQS, DQS#) option
- 4n-bit prefetch architecture
- Multiple internal device banks for concurrent operation
- Programmable CAS# latency (CL)
- Posted CAS# additive latency (AL)
- WRITE latency = READ latency - 1 tCK
