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MT5LC128K8D4 Datasheet Preview

MT5LC128K8D4 Datasheet

128K x 8 SRAM

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UICRON
1-·
"M',"OCOW, '"'
PRELIMINARY
MT5LC128K8D4
REVOLUTIONARY PINOUT 128K x 8 SRAM
SRAM
FEATURES
• All I/O pins are SV tolerant
• High speed: IS, 20 and 2Sns
• Multiple center power and ground pins for greater
noise immunity
• Easy memory expansion with CE and OE options
• Automatic CE power down
• All inputs and outputs are TIL-compatible
• High-performance, low-power, CMOS double-metal
process
• Single 3.3V ±O.3V power supply
• Fast OE access times: 10 and 12ns
• Complies to JEDEC low-voltage TTL-standards
OPTIONS
• Timing
ISns access
20ns access
2Sns access
• Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
MARKING
-IS
-20
-2S
DJ
TG
• 2V data retention
L
• Temperature
Commercial (O°C to +70°C)
Industrial (-40°C to +8S°C)
Automotive (-40°C to +12S°C)
Extended (-SSOC to +12S°C)
None
IT
AT
XT
• Part Number Example: MTSLC128K8D4DJ-20
NOTE: Not all combinations of operating temperature, speed, data retention
and lowpower are necessarily available. Please contact the factory for availabil-
ity of specific part number combinations.
128K X 8 SRAM
3.3V OPERATION WITH SINGLE CHIP
ENABLE, REVOLUTIONARY PINOUT
PIN ASSIGNMENT (Top View)
32-Pin SOJ
(SD-5)
32-Pin TSOP
(SE-1 )
A3
A2
A1
AD
CE
001
002
Vee
Vss
003
004
WE
A16
A15
A14
A13
A4
A5
A6
A?
OE
DOB
DO?
Vss
Vee
006
005
A8
A9
A1D
A11
A12
A3
A2
A1
AD
CE
001
002
Vee
Vss
003
004
WE
A16
A15
A14
A13
A4
A5
A6
A?
OE
DOB
DO?
Vss
Vee
006
005
AB
A9
A1D
A11
A12
(,,)
(,,)
0<
!:i
en
:»IJ
S
GENERAL DESCRIPTION
The MTSLC128K8D4 is organized as a 131,072 x 8 SRAM
using a fOUf-transistor memory cell with a high-speed, low-
power CMOS process. Micron SRAMs are fabricated using
double-layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, Micron
offers chip enable (CE) and output enable (OE) capability.
This enhancement can place the output in High-Z for
additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE) and chip enable inputs are both LOW. Reading
is accomplished when WE remains HIGH and CE goes
LOW. The device offers a reduced power standby mode
when disabled. This allows system designers to achieve
their low standby power requirements.
All devices operate from a single +3.3V power supply
and all inputs and outputs are fully TTL-compatible and SV
tolerant. These low-voltage parts are ideal for mixed 3.3V
and SV systems.
MT5LC12SK8D4
REV. 12193
2-75
Micron Semiconductor, tnc., reserves the right to change products or specifications without notice.
©1993, Micron Semiconductor, Inc.




Micron

MT5LC128K8D4 Datasheet Preview

MT5LC128K8D4 Datasheet

128K x 8 SRAM

No Preview Available !

MU::I=ION
1-' "
PRELIMINARY
MT5LC128K8D4
REVOLUTIONARY PINOUT 128K x 8 SRAM
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en
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AO
FUNCTIONAL BLOCK DIAGRAM
Vee GND
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Das
a:
W
aw:
ll.
ll.
~
C
u0w
C
1,048,576-BIT
MEMORY ARRAY
m
caeewnn:
3:
0a:
C
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....J
0a:
lz-
0
U
~
Da1
CE
COLUMN DECODER
POWER
DOWN
OE
WE
TRUTH TABLE
MODE
1Jf "CE WE" DO
POWER
STANDBY
X H X HIGH-Z STANDBY
READ
LLH
Q
ACTIVE
NOT SELECTED H L H HIGH-Z ACTIVE
WRITE
X L L D ACTIVE
MT5LC128K804
REV. 12193
2-76
Micron Semiconductor, Inc., flI88MI8 the rlght to change proWcts or specifications without nallce.
@1993,MlcronSemiconduc:lor,lnc.


Part Number MT5LC128K8D4
Description 128K x 8 SRAM
Maker Micron
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MT5LC128K8D4 Datasheet PDF






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