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MT5LC1008 Datasheet Preview

MT5LC1008 Datasheet

128K x 8 SRAM

No Preview Available !

ADVANCE
SRAM
FEATURES
• All I/O pins are 5V tolerant
• High speed: 15, 17, 20, 25, 35 and 45ns
• High-performance, low-power, CMOS double-metal
process
• Single +3.3V ±0.3V power sUPN
_
• Easy memory expansion with CE1, CE2 and OE
options
• All inputs and outputs are TTL-compatible
• Fast OE access time: 8ns
• Complies to JEDEC low-voltage TTL standards
OPTIONS
• Timing
15ns access
17ns access
20ns access
25ns access
35ns access
45ns access
MARKING
-15
-17
-20
-25
-35
-45
• Packages
Plastic DIP (400 mil)
Plastic SOJ (400 mil)
Plastic SOJ (300 mil)
• 2V data retention
• 2V data retention, low power
None
DJ
SJ
L
LP
• Temperature
Commercial (O°C to +70°C)
Industrial (-40°C to +85°C)
Automotive (-40°C to +125°C)
Extended (-55°C to +125°C)
None
IT
AT
XT
• Part Number Example: MT5LClO08DJ-35 LP
NOTE: Not all combinations of operating temperature, speed, data retention
and low power are necessarily available. Please contact the factory for availabil-
ity of specific part number combinations.
GENERAL DESCRIPTION
The MT5LC1008 is organized as a 131,072 x 8 SRAM
using a four-transistor memory cell with a high-speed, low-
power CMOS process. Micron SRAMs are fabricated using
double-layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Micron offers dual chip enables (CE1, CE2). This enhance-
ment can place the outputs in High-Z for additional
flexibility in system design.
Writing to these devices is accomplished when write
enable (WE) and CE1 inputs are both LOW and CE2 is
128Kx 8 SRAM
LOW VOLTAGE WITH OUTPUT
ENABLE
PIN ASSIGNMENT (Top View)
32-Pin DIP
(SA-6)
32-Pin SOJ
(SD-4)
(SD-5)
Ne
A16
A14
A12
A7
A6
AS
A4
A3
A2
A1
AD
DQ1
DQ2
DQ3
V"
3
4
5
8
9
10
11
12
13
14
15
16
32 Vco
31 A1S
30 eE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 eE1
21 DQ8
20 DQ7
19 DQ6
18 DQS
17 DQ4
Ne
A16 2
A14 3
A12 4
A7 5
A6 6
AS 7
A4 6
A3 9
A2 10
A1 11
AO 12
DQ1 13
DQ2 14
DQ3 15
V" 16
32 Vce
31 A1S
30 eE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 DE
23 A10
22 eE1
21 DQ8
20 DO?
19 DQ6
18 DQ5
17 004
w(,,)
o<
!:t
en
»s::D
HIGH. Reading is accomplished when WE and CE2 remain
HIGH and CE1 goes LOW. The device offers reduced
power standby modes when disabled. These modes allow
system designers to meetlow standbypowerrequirements.
The "LP" version provides a reduction in both CMOS
standby current (IsB2) and TTL standby current (ISBl) over
the standard part. This is achieved through the use of gated
inputs on the WE, OE and address lines. The gated inputs
also facilitate the design of battery-backed systems where
the designer needs to protect against inadvertent battery
current drain during power-down, when inputs may be at
undefined levels.
All devices operate from a single +3.3V power supply
and all inputs and outputs are fully TTL-compatible and 5V
tolerant. These low-voltage parts are ideal for mixed 3.3V
and 5V systems.
MT5lC1008
REV. 12193
2-67
Micron Semiconductor, Inc., reserves the right to change products or speCifications without notice.
©1993, Micron Semiconductor, Inc.




Micron

MT5LC1008 Datasheet Preview

MT5LC1008 Datasheet

128K x 8 SRAM

No Preview Available !

ADVANCE
FUNCTIONAL BLOCK DIAGRAM
Vee GND
AO-A16
a:
oooUJ
oUJ
eenn
ooa«U:J
1,048,576-BIT
MEMORY ARRAY
t-----, D08
o...J
a:
I-
oZ
o ._----" DOl
~
IO----1~ CEl
I - - - r . - CE2
Io--+-H- OE
,,---J:::!:+t- WE
POWER 1------'
DOWN 1--_---'
TRUTH TABLE
MODE
STANDBY
STANDBY
READ
NOT
SELECTED
WRITE
or ill CE2 WE DQ
POWER
X H X X HIGH-Z STANDBY
X X L X HIGH-Z STANDBY
L LHH
0
ACTIVE
H L H H HIGH-Z ACTIVE
X L H L D ACTIVE
MT5LC1008
REV. 12193
2-68
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1993, Micron Semiconductor, Inc.


Part Number MT5LC1008
Description 128K x 8 SRAM
Maker Micron
Total Page 8 Pages
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