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MT5LC1005 Datasheet Preview

MT5LC1005 Datasheet

256K x 4 SRAM

No Preview Available !

ADVANCE
SRAM
FEATURES
• All I/O pins are 5V tolerant
• High speed: 15, 17, 20, 25, 35 and 45ns
• High-performance, low-power, CMOS double-metal
process
• Single +3.3V ±0.3V power supply
• Easy memory expansion with CE and OE options
• All inputs and outputs are TTL-compatible
• Fast OE access time: 8ns
• Complies to JEDEC low-voltage TTL standards
OPTIONS
• Timing
15ns access
17ns access
20ns access
25ns access
35ns access
45ns access
MARKING
-15
-17
-20
-25
-35
-45
• Packages
Plastic DIP (400 mil)
Plastic SOJ (400 mil)
Plastic SOJ (300 mil)
• 2V data retention
• 2V data retention, low power
None
DJ
SJ
L
LP
• Temperature
Commercial (O°C to +70°C)
Industrial (-40°C to +85°C)
Automotive (-40°C to +125°C)
Extended (-55°C to +125°C)
None
IT
AT
XI
• Part Number Example: MT5LClO05DJ-35 LP
NOTE: Not all combinations of operating temperature, speed, data retention
and low power arenecessarily available. Please contactthe factory for availabil-
ity of specific part number combinations.
GENERAL DESCRIPTION
The MT5LCI005 is organized as a 262,144 x 4 SRAM
using a four-transistor memory cell with a high-speed, low-
power CMOS process. Micron SRAMs are fabricated using
double-layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Micron offers chip enable (CE) capability. This enhance-
ment can place the outputs in High-Z for additional
flexibility in system design.
256Kx4 SRAM
LOW VOLTAGE WITH OUTPUT
ENABLE
PIN ASSIGNMENT (Top View)
28-Pin DIP
(SA-5)
A? 1
'-/ 28 Vee
A8 2
27 AS
A9 3
26 AS
Al0 4
25 A4
All 5
24 A3
A12 6
23 A2
A13 7
22 Al
A14 8
21 AO
A1S 9
20 NC
A1S 10
19 D04
Al? 11
18 D03
CE 12
17 D02
OE 13
Vss 14
16 D01
-
15 WE
28-Pin SOJ
(SD-3)
(SD-2)
A7 [ 1
AB[ 2
A9 [ 3
A1D [ 4
A11 [ 5
A12 [ 6
A13 [ 7
A14 [ 8
A1S [ 9
AlB [ 10
A17 [ 11
GE[ 12
DE[ 13
Vss [ 14
28 Vee
27 AS
26 AS
25 A4
24 A3
23 A2
22 Al
21 AD
20 NC
19 D04
P18 D03
P17 D02
16 p~l
15 WE
(,,)
W
o<
~
en
:»s:D:
Writing to this device is accomplished when write enable
(WE) and CE inputs are both LOW. Reading is accom-
plished when WE remains HIGH while output enable (OE)
and CE are LOW. The device offers a reduced power stand-
by mode when disabled. This allows system designers to
meet low standby power requirements.
The "LP" version provides a reduction in both CMOS
standby current (ISB2) and TTL standby current (ISBl) over
the standard part. This is achieved through the use of gated
inputs on the WE, OE and address lines, which also facili-
tates the design of battery-backed systems. That is, the
gated inputs simplify the design effort and circuitry re-
quired to protect against inadvertent battery current drain
during power-down, when inputs may be at undefined
levels.
All devices operate from a single +3.3V power supply
and all inputs and outputs are fully TTL-compatible and 5V
tolerant. These low-voltage parts are ideal for mixed 3.3V
and 5V systems.
MT5LC1005
REV. 12193
2-33
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1993, Micron Semiconductor, Inc.




Micron

MT5LC1005 Datasheet Preview

MT5LC1005 Datasheet

256K x 4 SRAM

No Preview Available !

III
ww
o<
!:i
en
»s::D:
FUNCTIONAL BLOCK DIAGRAM
Vee GND
AO-A17
aw:
0
0
(w)
0
C/)
aCw/:)
0
«0
1,048,576-BIT
MEMORY ARRAY
-.J
0a:
I-
Z
0
()
~
ADVANCE
DQ4
DQ1
POWER
DOWN
MT5LC1005
REV. 12193
TRUTH TABLE
MODE
or CE WE
00
POWER
STANDBY
X H X HIGH-Z STANDBY
READ
L L H Q ACTIVE
NOT SELECTED H L H HIGH-Z ACTIVE
WRITE
X L L D ACTIVE
2-34
Micron Semiconductor, Inc" reS9IVes the right to change products or specifications without notice.
©1993, Micron Semiconductor, Inc.


Part Number MT5LC1005
Description 256K x 4 SRAM
Maker Micron
Total Page 8 Pages
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