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MT5LC1001 Datasheet Preview

MT5LC1001 Datasheet

1-Meg x 1 SRAM

No Preview Available !

ADVANCE
SRAM
FEATURES
• All I/O pins are 5V tolerant
• High speed: 15, 17, 20, 25, 35 and 45ns
• High-performance, low-power, CMOS double-metal
process
• Single +3.3V ±0.3 power supply
• Easy memory expansion with CE option
• All inputs and outputs are TTL-compatible
• Complies to JEDEC low-voltage TTL standards
OPTIONS
MARKING
• Timing
15ns access
17ns access
20ns access
25ns access
35ns access
45ns access
-15
-17
-20
-25
-35
-45
• Packages
Plastic DIP (400 mil)
Plastic SOJ (400 mil)
Plastic SOJ (300 mil)
None
DJ
SJ
• 2V data retention
• 2V data retention, low power
L
LP
• Temperature
Commercial (O°C to +70°C)
Industrial (-40°C to +85°C)
Automotive (-40°C to +125°C)
Extended (-55°C to +125°C)
None
IT
AT
XT
• Part Number Example: MT5LClOOIDJ-25 L
NOTE: Not all combinations of operating temperature, speed, data retention
and lowpower arenecessarily available. Please contact the factory for availabil-
ity of specific part number combinations.
GENERAL DESCRIPTION
The MT5LClOOl is organized as a 1,048,576 x 1 SRAM
using a four-transistor memory cell with a high-speed, low-
power CMOS process. Micron SRAMs are fabricated using
double-layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Micron offers chip enable (CE) capability. This enhance-
ment can place the outputs in High-Z for additional
flexibility in system design.
Writing to this device is accomplished when write enable
(WE) and CE inputs are both LOW. Reading is accom-
1 MEGx 1 SRAM
LOW VOLTAGE
PIN ASSIGNMENT (Top View)
28-Pin DIP
(SA-5)
AlO 1 ~ 28 Vee
A11 2
27 A9
A12 3
26 AS
A13 4
25 A7
A14 5
24 AS
A15 6
23 AS
NC 7
22 A4
A16 8
21 NC
A17 9
20 A3
A18 10
19 A2
A19 11
18 Al
Q 12
WE 13
V.. 14
17 AO
16 D
15 CE
28-Pin SOJ
(SD-3)
(SD-2)
A10
A11
A12 3
A13 4
A14 5
A15 6
NC
A16
A17 9
A1S 10
A19 11
Q 12
WE 13
Vss 14
28 Vee
27 A9
26 AS
25 A7
24 A6
23 A5
22 A4
21 NC
20 A3
19 A2
18 A1
17 AO
16 D
15 BE
WW
<
0
!:f
en
::D
l>
3:
plished when WE remains HIGH while CE goes LOW. The
device offers a reduced power standby mode when dis-
abled. This allows system designers to meet low standby
power requirements.
The "LP" version provides a reduction in both CMOS
standby current (ISB2) and TTL standby current (ISB1) over
the standard part. This is achieved through the use of gated
inputs on the WE and address lines, which also facilitates
the design of battery-backed systems. That is, the gated
inputs simplify the design effort and circuitry required to
protect against inadvertent battery current drain during
power-down, when inputs may be at undefined levels.
All devices operate from a single +3.3V power supply
and all inputs and outputs are fully TTL-compatible and 5V
tolerant. These low-voltage parts are ideal for mixed 3.3V
and 5V systems.
MT5LC1001
REV. 12193
2-9
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1993, Micron Semiconductor,lnc.




Micron

MT5LC1001 Datasheet Preview

MT5LC1001 Datasheet

1-Meg x 1 SRAM

No Preview Available !

ADVANCE
FUNCTIONAL BLOCK DIAGRAM
w
W
o<
!:i
en
:D
sl>:
AO-A19
a:
oow
()
ow
(/)
(/)
oo«aw:
Vee GND
1,048,576-BIT
MEMORY ARRAY
1----< f---- D
1----+-1 >---- Q
o- l
a:
I-
oZ
10--__._- CE
()
~
+----*-+- WE
POWER
DOWN
TRUTH TABLE
MODE
STANDBY
READ
WRITE
cr- WE
INPUT
H X DON'T CARE
L H DON'T CARE
LL
DATA-IN
OUTPUT
HIGH-Z
Q
HIGH-Z
POWER
STANDBY
ACTIVE
ACTIVE
MT5LC1(}OI
REV.I2f93
2-10
Micron Semiconductor, Inc., reselVes the right 10 change products or specificatiQns without notice
©1993, Micron Semiconductor, Inc


Part Number MT5LC1001
Description 1-Meg x 1 SRAM
Maker Micron
Total Page 8 Pages
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