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MT4LC1M16C3 - 1 MEG x 16 FPM DRAM

Download the MT4LC1M16C3 datasheet PDF. This datasheet also covers the MT4C1M16C3 variant, as both devices belong to the same 1 meg x 16 fpm dram family and are provided as variant models within a single manufacturer datasheet.

General Description

The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration.

The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#).

Key Features

  • JEDEC- and industry-standard x16 timing, functions, pinouts, and packages.
  • High-performance, low-power CMOS silicon-gate process.
  • Single power supply (+3.3V ±0.3V or 5V ±0.5V).
  • All inputs, outputs and clocks are TTL-compatible.
  • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN.
  • Optional self refresh (S) for low-power data retention.
  • BYTE WRITE and BYTE READ access cycles.
  • 1,024-cycle refresh (10 row, 10 column add.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MT4C1M16C3-Micron.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Micron Technology

Part Number Description
MT4LS12832 128K x 32 SRAM MODULE
MT4LSDT1664A 128MB SDRAM Unbuffered DIMM
MT4LSDT1664H 128MB SMALL-OUTLINE SDRAM MODULE
MT4LSDT1664LH 128MB SMALL-OUTLINE SDRAM MODULE
MT4LSDT464A 32MB SDRAM Unbuffered DIMM
MT4LSDT464H 32MB SMALL-OUTLINE SDRAM MODULE
MT4LSDT464LH 32MB SMALL-OUTLINE SDRAM MODULE
MT4LSDT864A 64MB SDRAM Unbuffered DIMM
MT4LSDT864H 64MB SMALL-OUTLINE SDRAM MODULE
MT4LSDT864LH 64MB SMALL-OUTLINE SDRAM MODULE

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
1 MEG x 16 FPM DRAM FPM DRAM FEATURES • JEDEC- and industry-standard x16 timing, functions, pinouts, and packages • High-performance, low-power CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or 5V ±0.5V) • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN • Optional self refresh (S) for low-power data retention • BYTE WRITE and BYTE READ access cycles • 1,024-cycle refresh (10 row, 10 column addresses) • FAST-PAGE-MODE (FPM) access MT4C1M16C3, MT4LC1M16C3 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.