The TP2424 low-threshold Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process.
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TP2424 P-Channel Enhancement-Mode Vertical DMOS FET Features • Low Threshold • High Input Impedance • Low Input Capacitance • Fast Switching Speeds • Free from Secondary ...
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• Low Input Capacitance • Fast Switching Speeds • Free from Secondary Breakdown • Low Input and Output Leakage Applications • Logic-Level Interfaces (Ideal for TTL and CMOS) • Solid-State Relays • Linear Amplifiers • Analog Switches • Power Management • Telecommunication Switches General Description The TP2424 low-threshold Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS
TP2424 Datasheet
