TN5325 Datasheet | Microchip Technology

TN5325 N-Channel Enhancement-Mode Vertical DMOS FET Features - Low Threshold (2V Maximum) - High Input Impedance and High Gain - Free from Secondary Breakdown - Low CISS and Fast Switching Speeds Applications - Logic-level Interfaces (Ideal for TTL and CMOS) - Solid State Relays - Battery-operated Systems - Photo-voltaic Drives - Analog Switches - General Purpose Line Drivers - Telemunication Switches General Description The TN5325 is a low-threshold, Enhancement-mode (normally-off) transistor that utilizes a vertical DMOS structure and a well-proven silicon gate manufacturing process. This bination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Microchip’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance and fast switching speeds are desired. Package Types 3-lead SOT-23 (TO-236AB) (Top view) DRAIN 3-lead TO-92 (Top view) 3-lead SOT-89 (243AA) (Top view) DRAIN SOURCE GATE SOURCE DRAIN See Table 2-1, Table 2-2 and Table 2-3 for pin information. GATE SOURCE DRAIN GATE...