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PIC18F25K40 Datasheet

Memory Programming Specification

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PIC18(L)F2X/4XK40
PIC18(L)F2X/4XK40 Memory Programming Specification
1.0 OVERVIEW
This programming specification describes an SPI-based programming method for the PIC18(L)F2X/4XK40 family of
microcontrollers. Section 3.0 “Programming Algorithms” describes the programming commands, programming
algorithms and electrical specifications which are used in that particular programming method. Appendix B contains
individual part numbers, device identification and checksum values, pinout and packaging information and Configuration
Words.
Note 1: This is a SPI-compatible programming method with 8-bit commands.
2: The low-voltage entry code is now 32 clocks and MSb first, unlike previous PIC18 devices which had 33
clocks and LSb first.
1.1 Programming Data Flow
Nonvolatile Memory (NVM) programming data can be supplied by either the high-voltage In-Circuit Serial
Programming™ (ICSP™) interface or the low-voltage In-Circuit Serial Programming (ICSP) interface. Data can be
programmed into the Program Flash Memory (PFM), Data Flash Memory (EEPROM), dedicated “user ID” locations and
the Configuration Words.
1.2 Write and/or Erase Selection
Erasing or writing is selected according to the command used to begin operation (see Table 3-1). The terminologies
used in this document related to erasing/writing to the program memory are defined in Table 1-1 and are detailed below.
TABLE 1-1: PROGRAMMING TERMS
Term
Definition
Programmed Cell
Erased Cell
Erase
Write
Program
A memory cell at logic ‘0
A memory cell at logic ‘1
Change memory cell from a ‘0’ to a ‘1
Change memory cell from a ‘1’ to a ‘0
Generic erase and/or write
1.2.1 ERASING MEMORY
Memory is erased by row or in bulk, where ‘bulk’ includes many subsets of the total memory space. The duration of the
erase is determined by the size of program memory. All Bulk ICSP Erase commands have minimum VDD requirements,
which are higher than the Row Erase and write requirements.
1.2.2 WRITING MEMORY
Memory is written one row at a time. Multiple Load Data for NVM commands are used to fill the row data latches. The
duration of the write can be determined either internally or externally.
1.2.3 MULTI-WORD PROGRAMMING INTERFACE
Program Flash Memory (PFM) panels include up to a 64-word (one row) programming interface. Refer to Table 3-3 for
row size of erase and write operations for the PIC18(L)F2X/4XK40 family. The row to be programmed must first be
erased either with a Bulk Erase or a Row Erase.
2014 Microchip Technology Inc.
DS40001772A-page 1


  Microchip Technology Semiconductor Electronic Components Datasheet  

PIC18F25K40 Datasheet

Memory Programming Specification

No Preview Available !

PIC18(L)F2X/4XK40
1.3 Hardware Requirements
1.3.1 HIGH-VOLTAGE ICSP PROGRAMMING
In High-Voltage ICSP mode, the device requires two programmable power supplies: one for VDD and one for the MCLR/
VPP pin.
1.3.2 LOW-VOLTAGE ICSP PROGRAMMING
In Low-Voltage ICSP mode, the device can be programmed using a single VDD source in the operating range. The
MCLR/VPP pin does not have to be brought to programming voltage, but can instead be left at the normal operating
voltage.
1.3.2.1 Single-Supply ICSP Programming
The device’s LVP Configuration bit enables single-supply (low-voltage) ICSP programming. The LVP bit defaults to a ‘1
(enabled). The LVP bit may only be programmed to ‘0’ by entering the High-Voltage ICSP mode, where the MCLR/VPP
pin is raised to VIHH. Once the LVP bit is programmed to a ‘0’, only the High-Voltage ICSP mode is available and only
the High-Voltage ICSP mode can be used to program the device.
Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH
to the MCLR/VPP pin.
2: While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit, and the port
pin can no longer be used as a general purpose input.
1.4 Pin Utilization
Five pins are needed for ICSP programming. The pins are listed in Table 1-2. For pin locations and packaging
information please refer to Table B-3.
TABLE 1-2: PIN DESCRIPTIONS DURING PROGRAMMING
Pin Name
Function
During Programming
Pin Type
Pin Description
ICSPCLK
ICSPCLK
I Clock Input – Schmitt Trigger Input
ICSPDAT
MCLR/VPP
ICSPDAT
Program/Verify mode
I/O Data Input/Output – Schmitt Trigger Input
I(1) Program Mode Select
VDD VDD P Power Supply
VSS VSS P Ground
Legend:
Note 1:
I = Input, O = Output, P = Power
The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage
needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any
significant current.
DS40001772A-page 2
2014 Microchip Technology Inc.


Part Number PIC18F25K40
Description Memory Programming Specification
Maker Microchip
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